1. Field of the Invention
The present invention relates to a multiplier circuit, particularly to a linear multiplier circuit which has a better linearity between its input and output signals.
2. Description of the Prior Art
An analog multiplier is a circuit that can receive two input signals in analog form and generate an output signal proportional in magnitude to the product of the two input signals. The input signals are typically voltages, in which case the analog multiplier is customarily referred to as a voltage-mode analog multiplier. An analog multiplier can be organized either as a two-quadrant or a four-quadrant circuit. The product signal output by the analog multiplier circuit may be converted into a digital format by means of an analog-to-digital (A/D) output stage.
Analog multipliers are used in many different applications, such as modulators, phase comparators, adaptive filters, AC-to-DC converters, and sine/cosine synthesizers, to name just a few. Moreover, analog multipliers have found used in fuzzy logic controllers and artificial neural networks. In some applications it is necessary that the multiplier yield linear products of both inputs. Linear products of both inputs are easily achieved in the digital domain. However, analog multiplier circuits have a disadvantage in that they exhibit poor linearity. Improvements on the linearity of analog multipliers are difficult and expensive to achieve, particularly where the multipliers are solid-state multipliers such as those implemented in CMOS technology. This typically results in considerable cost over an analog implementation in the form of A/D and D/A converters and in general with a larger power consumption and chip area than those of an analog implementation.